The availability of inexpensive semiconductor memory has made it possible to provide computing systems which are vastly more powerful, but nevertheless smaller and less expensive than their predecessors. While such memory has significantly contributed to the advancement of the computer art, it is not without problems. For example, the manufacturing techniques used to fabricate such memory are not capable of yielding completely error free chips in sufficient quantity to make it economically feasible to discard those with only a few defects. Various techniques have been employed to accommodate this inadequacy. Extra storage positions to replace those found to be defective and automatic reassignment of the bad addresses to another location are examples of such approaches to the problem.
While these approaches are effective for most of the general purpose storage requirements in computing systems, there are occasions where it is necessary to have a completely error free portion of memory. Generally, this portion must extend from the very lowest memory address in unbroken fashion, to the highest address required to provide the requisite storage capacity. An example of such a requirement exists in the IBM System 38. The System 38 uses an area of storage for predetermined tasks whose addresses are based on pointers, and cannot tolerate a bad area of storage. The requirement that the Control Address Table and the Primary Directory be free from uncorrectable errors was handled by service personnel during installation of the system. The results of memory test were evaluated by the person doing the installation and memory cards were replugged to provide the requisite error free storage at the desired addresses.
The problem is complicated on systems which utilize paired memory cards. This may require that a good card paired with a bad one must be removed along with the bad one when the replugging is done.
The traditional "installation" of a computer system by skilled service personnel has become a thing of the past for all but the largest computer systems. The size of the typical computing system has become such that the customer may actually carry the computer from the store, and the cost has been correspondingly reduced to the point where the added expense of service personnel for installation is no longer economically feasible.
The memory test, unplugging and replugging of memory cards and reconfiguration formerly performed by trained service personnel are far too complex to be performed by the average customer.
Attempts to solve this problem have been ineffective. While the memory test operation has been effectively automated, and improvements made in the substitutability of memory cards; for example, paired cards can be exchanged by operation of a switch instead of physically interchanging them; a comprehensive approach to the entire problem has been lacking.
Various systems and techniques for testing memory have been shown in IBM Technical Disclosure Bulletin, 1979, Vol. 11, pp. 2377-2379; IBM Technical Disclosure Bulletin, 1981, Vol. 12, p. 3268; IBM Technical Disclosure Bulletin, 1982, Vol. 1, pp. 4417-4424; IBM Technical Disclosure Bulletin, 1984, Vol. 5, pp. 5996-6000; IBM Technical Disclosure Bulletin, 1984, Vol. 9, pp. 2045-2046; IBM Technical Disclosure Bulletin: 1986, Vol. p. 2390; IBM Technical Disclosure Bulletin, 1987, Vol. 1, pp. 3474-3475; and IBM Technical Disclosure Bulletin , 1987, Vol. 1, pp. 3622-3625.
U.S. Pat. No. 4,070,704 relates to a system in which the initial program load of a system is reinitiated in the event of failure to properly complete. If the system fails to boot properly, it is reconfigured and another IPL is attempted. The configuration organization is determined by the state of a sequential counter. The system steps through all possible configurations until one is found which allows the IPL to proceed to successful completion.
U.S. Pat. No. 4,507,730 deals with the problems of reconfiguring memory serviced by a controller to provide a contiguous error-free portion by rearranging the memory serviced by the controller to place the bad bit positions at the upper portion of that memory. Each controller can be reconfigured to respond to a different address on the address bus, which requires that a reconfiguration command be issued to all the controllers and special purpose circuitry be located in each controller to implement this command.